The present invention relates generally to non-volatile memory devices and, in particular, the present invention relates to erase operations of flash memories.
A flash memory device is a non-volatile memory, derived from erasable programmable read-only memory (EPROM) and electrically-erasable programmable read-only memory (EEPROM). Flash memory is being increasingly used to store execution codes and data in portable electronic products, such as computer systems.
A typical flash memory comprises a memory array having a large number of memory cells arranged in blocks. Each of the memory cells is fabricated as a field-effect transistor having a control gate and a floating gate. The floating gate is capable of holding a charge, and is separated, by a layer of thin oxide, from source and drain regions contained in a substrate. Each of the memory cells can be electrically programmed (charged) by injecting electrons from the drain region through the oxide layer onto the floating gate. The charge can be removed from the floating gate by tunneling the electrons to the source through the oxide layer during an erase operation. Thus the data in a memory cell is determined by the presence or absence of a charge on the floating gate.
Flash memories have a typical operating voltage of about 5 volts. A high voltage, however, is usually required for programming and erase operations in a flash memory. This high voltage (Vpp) is in the range of the 10 to 13 volts, but can be higher. During a programming operation, electrons are injected onto the floating gate by applying the high voltage (Vpp) to the control gate and about one-half Vpp to the drain region while the source region is grounded. Electron tunneling from the floating gate during an erase operation is accomplished by applying Vpp to the source region, connecting the control gate to ground potential and leaving the drain region electrically unconnected or floating.
As with any device, a flash memory has a limited useful life. The useful s life of a flash memory is defined by its cycling specification. A flash memory""s cycling specification is the maximum number of program/erase cycles which a flash memory is expected to perform without loss of preset margin. This number is normally about 100,000 cycles. When a specific flash memory exceeds the specified cycling number, the device could suffer from undesirable performance, or even permanent damage. The oxide layer between the floating gate and the substrate tends to be the limiting element in increasing memory life. The oxide layer is an insulator which is used to transport carriers (electrons or holes) to the floating gates to change data states. This transportation is the greatest cause of degraded performance. The quality of the oxide used and how well the oxide is treated during program and erase cycles are important factors in determining the cycling specification.
During an erase cycle, the high voltage (Vpp) applied across the oxide causes tunneling of electrons from the floating gate to the source. At the same time, the high voltage could cause holes from the source to be injected into the oxide. These holes can degrade the performance of the oxide by creating a leakage path in the oxide between the source and the floating gate.
Since the oxide is the barrier for electrons traveling to and from the floating gate, the charging and discharging current of a memory cell depends on the voltage applied across the oxide layer, I=C(dv/dt). Therefore, the voltage applied across the oxide has a direct effect on electron tunneling and is the main cause of undesirable hole injection into the oxide during an erase operation. To improve the durability of the oxide and the reliability of the flash memory, there is a need for a method and circuit to regulate the voltage applied across the oxide of the memory cell during an erase operation.
The present invention describes a circuit and method for improving the reliability of a flash memory by regulating the voltage applying to the source of memory cells during an erase operation. By ramping the voltage applied to the source, the invention allows electron tunneling to occur while reducing the current through the floating gate oxide layer.
In particular, the present invention describes a memory comprising an array of floating gate memory cell transistors, and a control circuit. The control circuit, which by applying appropriate voltages to the array of floating gate memory cells, causes the cells to store a charge on the floating gate memory cell transistors during a programming operation, and remove the stored charge from the floating gate memory cell transistors during an erase operation. The memory also comprises a source regulation circuit for applying a ramped voltage signal to sources of the floating gate memory cell transistors during an erase operation.
In another embodiment, a flash memory is described which comprises a memory array of floating gate memory cell transistors, a differential amplifier having first and second inputs and an output, and a voltage divider circuit connected to the first input of the differential amplifier for providing a variable reference voltage. A voltage ramp generator is provided which has an output connected to the second input of the differential amplifier for providing a ramped reference voltage signal. An output circuit is connected to the output of the differential amplifier for providing a ramped voltage signal to be coupled to sources of the floating gate memory cell transistors during an erase operation.
In yet another embodiment, a method of erasing a floating gate memory cell transistor is described. The method comprises the steps of coupling a control gate of the floating gate memory cell transistor to a low voltage potential, and applying a ramped voltage signal to a source of the floating gate memory cell.
A method is described for improving reliability of a flash memory having memory cells formed as transistors. The memory cells have a floating gate separated from a channel region by a layer of gate oxide. The method comprises the steps of coupling a control gate of the memory cell to a low voltage potential, generating a pulsed ramped voltage signal, and applying the pulsed ramped voltage signal to a source of the memory cell.